This invention relates to a logic circuit and to a semiconductor integrated circuit device using the former, and more particularly to a logic circuit and a semiconductor integrated circuit device capable of operating by different power supplies and a semiconductor integrated circuit system constituted by coupling a plurality of semiconductor integrated circuit devices.
Since semiconductor technology has made a remarkable progress, the age of 0.5 .mu.m will arrive in the 1990s. It is said that in such an age of 0.5 .mu.m, the power source voltage must be reduced from the current voltage of 5 V to a lower voltage (e.g. 3 V).
In other words, the 0.5 .mu.m age will be an era where LSIs operating by the power supply of the 5 V system and semiconductor integrated circuit devices (LSIs) operating by the power supply of the 3 V system coexist, and LSIs operating at these two difference power source voltages exist in mixture inside an electronic circuit device constituted by coupling a pluralilty of LSIs.
FIG. 8(A) of the accompanying drawings shows the case where first LSI 811 and second LSI 812 operate at the same power supply level (e.g. 5V). In the drawing, reference numeral 813 represents an output signal line from LSI 811 to LSI 812 and reference numeral 814 represents an output signal line from LSI 812 to LSI 811.
FIG. 8(B) shows the case where LSI 812 operates at a first power supply voltage V.sub.1 while LSI 822 operates at a second power supply voltage V.sub.2 (V.sub.2 &lt;V.sub.1). Reference numeral 823 represents an output signal line from LSI 812 to LSI 822 while reference numeral 824 represents an output signal line from LSI 822 to LSI 821.
FIG. 8(C) shows the case where LSIs 831 and 832 operate at the first power supply voltage V.sub.1 while LSI 833 operates at the second power supply voltage V.sub.2.
Among the three cases described above, no problem occurs in the mutual interface by the signal lines 813 and 814 in the case of FIG. 8(A) because both LSIs operate at the same power supply level.
In the cases of FIGS. 8(B) and 8(C), however, the following problems might occur because any interface is necessary between LSIs that operate at different power supply levels.
FIG. 9 shows an interface of LSIs 910 and 920 constituted by an ECL circuit. In LSI 910, reference numerals 911 and 913 represent NPN transistors; 914 and 915 are resistors; 916 is a constant current circuit; and 917 is an output pin of LSI 910 which operates at a power supply -V.sub.1. The output level appearing at the output pin 917 is given as follows: EQU V.sub.OH =0-V.sub.BE =-0.8V EQU V.sub.OL =0-I.sub.EE .multidot.R.sub.2 -V.sub.BE =-1.6V
where
V.sub.BE : base-emitter voltage of NPN 913 PA1 I.sub.EE : current value of constant current circuit 916 PA1 R.sub.2 : resistance of resistor 914.
In other words, in the ECL circuit, the high level output V.sub.OH and the low level output V.sub.OL are determined irrespective of the level of the operation power supply. Therefore, LSI 920 can normally receive a signal from LSI 910 provided that a signal is received at the base of the NPN transistor 921 and a voltage of about -1.2 V, which is at an intermediate level between V.sub.OH and V.sub.OL, is applied as a reference voltage to the base of NPN transistor 922.
It is to be noted specifically from the description given above that there is no specific problem for the ECL circuit even if a plurality of LSIs operate at mutually different power supply voltages.
FIG. 10 shows an inverter circuit as an example of CMOS logic circuit, wherein 1001 is PMOS and 1002 is NMOS. When VIN is at the "1" level, the output VOUT is 0 for V. When VIN is at the "0" level, on the other hand, VOUT is at the same voltage as the power supply voltage V.sub.1.
FIG. 11 shows an inverter circuit as an example of BiCMOS logic circuit, wherein 1101 is PMOS; 1102 is NMOS; 1103 and 1104 are NPN bipolar transistors; and 1105 and 1106 are resistors. When VIN is at the "1" level, the output VOUT becomes 0 V. When VIN is at the "0" level, on the other hand, VOUT becomes the same voltage as the power supply voltage V.sub.1.
In the case of the CMOS and BiCMOS circuits described above, one of the output levels is substantially equal to the power supply voltage.
Therefore, when LSIs operating at different power supply voltages are connected with one another, the following problem develops.
FIG. 12 shows the case where the output of LSI 1210 operating at the power supply voltage V.sub.1 is applied to LSI 1220 operating at the power supply voltage V.sub.2 (V.sub.2 &lt;V.sub.1). In LSI 1210, reference numeral 1211 represents PMOS; 1212 is NMOS; 1213 is an internal circuit; 1214 and 1215 are parasitic diodes; and 1217 is an output pin. PMOS 1211 and NMOS 1212 together form the output circuit.
In LSI 1220, reference numeral 1221 represents PMOS; 1222 is NMOS; 1223 is an internal circuit performing a predetermined functional operation and preferably a logic operation; 1224 and 1225 are protective diodes; 1226 is a protective resistor; and 1227 is an input pin. PMOS 1221 and NMOS 1222 together form the input circuit, while the diodes 1224, 1225 and the resistor 1226 form the input protection circuit.
When LSI 1210 outputs the "1" level in this example, an abnormally large current keeps flowing through the path of power supply V.sub.1 --PMOS 1211 --resistor 1226 --diode 1224 --power supply V.sub.2 because V.sub.2 &lt;V.sub.1, so that the following problems occur in both LSIs 1210 and 1220.
(1) High power consumption occurs in PMOS 1211 in LSI 1210 due to the abnormal current and reliability drops, too.
(2) High power consumption occurs in the resistor 1226 and the diode 1224 in LSI 1220 due to the abnormal current and reliability drops, too.
FIG. 13 shows the case where the output of LSI 1310 operating at the power supply voltage V.sub.1 and that of LSI 1320 operating at the power supply voltage V.sub.2 are connected to each other.
In LSI 1310, reference numeral 1311 represents PMOS; and 1312 is NMOS; 1314 and 1315 are parasitic diodes. PMOS 1311 and NMOS 1312 form a tri-state output circuit which is subjected to ON/OFF control by the input signals E.sub.1, E.sub.2. Reference numeral 1317 represents the output pin of LSI 1310.
In LSI 1320, reference numeral 1321 represents PMOS; 1322 is NMOS; and 1324 and 1325 are parasitic diodes. PMOSs 1321 and 1322 form a tri-state output circuit which is subjected to ON/OFF control by the input signals E.sub.3, E.sub.4.
In this example, both PMOS 1321 and NMOS 1322 are OFF when E.sub.3 is at the "1" level and E.sub.4 is at the "0" level and since an abnormally large current keeps flowing through the path of the power supply V.sub.1 --PMOS 1311 --diode 1324 --power supply V.sub.2 when both E.sub.1 and E.sub.2 are at the "0" level, the following problems occur in both LSIs 1310 and 1320.
(1) High power consumption occurs in PMOS 1311 in LSI 1310 due to the abnormal current and reliability drops, too.
(2) High power consumption occurs in the parasitic diode 1324 in LSI 1320 due to the abnormal current and reliability drops, too.
FIGS. 14 and 15 show examples of mutual connection using an open drain type output circuit in accordance with a prior art technique in order to prevent the flow of the abnormal current resulting from the mis-match of the power supply voltages.
FIG. 14 shows the case where the output of LSI 1410 operating at the power supply voltage V.sub.1 is an input of LSI 1420 operating at the power supply voltage V.sub.2 (V.sub.2 &lt;V.sub.1).
In LSI 1410, reference numeral 1411 represents NMOS; 1414 is a parasitic diode; 1415 is an internal circuit; and NMOS 1411 constitutes an open drain type output circuit. Reference numeral 1417 represents the output pin of LSI 1410.
In LSI 1420, reference numeral 1421 represents PMOS; 1422 is NMOS; 1423 and 1424 are protective diodes; 1426 is a protective diode; 1425 is an internal circuit; 1427 is the input pin of LSI 1420; and 1430 is a pullup resistor of the open drain output circuit 1411. One of the ends of this resistor is connected to the same power supply as the power supply V.sub.2 having a lower voltage and the other end is connected to the output pin 1417 and to the input pin 1427.
When the internal circuit 1415 outputs the "0" level in this example, NMOS 1411 is OFF, a load CL is charged from the power supply V.sub.2 through the resistor 1430 and the input pin 1427 of LSI 1420 is at the "1" level equal to the power supply V.sub.2.
Accordingly, no abnormal current flows at this time because the protective diode 1423 is not turned ON.
When the internal circuit 1415 outputs the "1" level, on the other hand, NMOS 1411 is turned ON, the charge of the load CL is discharged through NMOS 1411 and the input pin 1427 of LSI 1420 is switched to the "0" level. At this time, the output "0" level is higher than 0 V because the D.C. current flows through the power supply V.sub.2, the resistor 1430 and NMOS 1411.
FIG. 15 shows the example where LSI 1510 operating at the power supply voltage V.sub.1 and LSI 1520 operating at the power supply voltage V.sub.2 are connected to each other by the open drain type output circuit.
In LSI 1510, reference numeral 1511 represents NMOS; 1514 is a parasitic diode; 1515 is an internal circuit which constitutes the open drain type output circuit; and 1517 is the output pin of LSI 1510.
In LSI 1520, reference numeral 1521 represents NMOS; 1524 is a parasitic diode; 1525 is an internal circuit; and NMOS 1521 constitutes the open drain type output circuit. Reference numeral 1530 represents a pullup resistor.
When NMOS 1521 of LSI 1520 is OFF and NMOS 1511 is OFF in LSI 1511 in this example, the load CL is charged from the power supply V.sub.2 through the resistor 1530, the potential of the input pin 1527 of LSI 1520 is equal to the potential of V.sub.2, and no abnormal current flows because both NMOS 1521 and the parasitic diode 1524 are OFF.
When NMOS 1511 is ON, on the other hand, the charge of the capacitance load LC is discharged through NMOS 1511 and the output pin 1517 is switched to the "0" level. Since the D.C. current flows through the power supply V.sub.2, the resistor 1530 and NMOS 1511 at this time, the output "0" level is higher than 0 V.
As described above, mutual connection by the open drain output can solve the problem of the abnormal current resulting from the mis-match of the power supply voltages, but is not free from the following problems. Firstly, the D.C. current flows when the output is at the "0" level so that the number of outputs is limited from the aspect of power consumption. The "0" level of the output is higher than 0 V and the output amplitude drops. Secondly, since the switching speed of the output to the "1" level is determined by the time constants of the pullup resistor and load capacitance, the transmission speed of signals is low and the application to a high speed system is therefore difficult. If the pullup resistance is reduced in order to improve the speed, power consumption due to the D.C. current becomes greater. Accordingly, both of the requirements for higher operation speed and lower power consumption cannot be satisfied simultaneously.
As described above, when LSIs operating at different power supply voltages are connected mutually in accordance with the prior art technique, the problems such as the occurrence of the abnormal current, the increase of power consumption and the increase of the delay time develop unavoidably.